The present invention relates to a semiconductor memory device having a plurality of banks, and, more particularly, to a semiconductor memory device which performs write and read operations on a selected bank and a refresh operation on non-selected banks in parallel.
The recent achievement of larger capacity and a greater number of bits demands the use of DRAMs each of which has a plurality of banks mounted on a same semiconductor substrate and performs write and read operations on a selected bank and a refresh operation on non-selected banks in parallel.
FIG. 1 is a schematic block diagram of a synchronous DRAM (SDRAM) 100 according to the prior art. The SDRAM 100 includes a plurality of banks MB0 to MBn mounted on a semiconductor substrate. The SDRAM 100 is independently accessable by the individual banks, so that each bank operates as an independent DRAM.
Each of the banks MB0-MBn includes a memory cell array having a plurality of memory cells, a memory cell select circuit which selects memory cells in accordance with an address signal, a data write circuit which writes cell information in selected memory cells and a data read circuit which reads cell information from selected memory cells.
The SDRAM 100 further includes refresh address counters RC0 to RCn corresponding to the banks MB0-MBn and a switch circuit SW1 connected between the refresh address counters RC0-RCn and the banks MB0-MBn. Every time the refresh address counters RC0-RCn receive a refresh request signal RQ, they generate refresh address signals RA00 to RA09, RA10 to RA19, and RAn0 to RAn9 of, for example, 10 bits corresponding to the banks MB0-MBn, through a count-up operation, and provide the refresh address signals to the switch circuit SW1.
The switch circuit SW1 receives external address signals EA0 to EA9 and bank control signals BC0 to BCn from external circuits and supplies address signals A00 to A09, A10 to A19, and An0 to An9 to the respective banks MB0-MBn via ten respective signal lines. The external address signals EA0-EA9 are used to perform a write operation or read operation with respect to the banks MB0-MBn. The bank control signals BC0-BCn are used to select any bank on which a write operation or read operation is to be performed.
The switch circuit SW1 selects, for example, the address signals A00-A09 provided to the bank MB0 from the external address signals EA0-EA9 and the refresh address signals RA00-RA09. Likewise, the switch circuit SW1 selects the address signals A10-A19 provided to the bank MB1 from the external address signals EA0-EA9 and the refresh address signals RA10-RA19. Further, the switch circuit SW1 selects the address signals An0-An9 provided to the bank MBn from the external address signals EA0-EA9 and the refresh address signals RAn0-RAn9.
The operation of the SDRAM 100 will be discussed referring to FIG. 2. The individual banks MB0-MBn operate in synchrony with an external clock signal CLK. When an active signal ACTV is provided to the bank MB0 at a first timing t1 and the bank control signal BC0 is provided to the switch circuit SW1, for example, the switch circuit SW1 selects the external address signals EA0-EA9 and provides the selected external address signals (address signals A00-A09) to the bank MB0. The bank MB0 is enabled by the active signal ACTV and executes a write operation or a read operation in accordance with the external address signals EA0-EA9.
At the same time, the refresh request signal RQ is provided to each of the refresh address counters RC0-RCn. Each of the refresh address counters RC0-RCn performs the count-up operation and provides a refresh address signal to the switch circuit SW1.
The switch circuit SW1 provides refresh address signals (address signals A10-A19, An0-An9) to the non-selected banks MB1-MBn to perform a refresh operation of the cell information.
When the active signal ACTV is provided to the bank MB1 at a second time t2 and the bank control signal BC1 is provided to the switch circuit SW1, the switch circuit SW1 provides the external address signals EA0-EA9 (address signals A10-A19) to the bank MB1. The bank MB1 is enabled by the active signal ACTV and performs a write operation or a read operation in accordance with the external address signals EA0-EA9.
At the same time, the switch circuit SW1 respectively provides refresh address signals to the non-selected banks MB0 and MB2-MBn to refresh cell information. Thereafter, such a write operation or a read operation and refresh operation are repeated.
When a self-refresh command is provided to the individual banks MB0-MBn, the refresh request signal RQ which is generated within the chip is provided to the individual refresh address counters RC0-RCn. Then, the refresh address signals provided from the refresh address counters RC0-RCn are provided to the respective banks MB0-MBn via the switch circuit SW1, and all of the banks MB0-MBn perform a refresh operation simultaneously.
The SDRAM 100 requires that the same number of address signal lines as the number of bits of the address signals should be laid between the switch circuit SW1 and the banks MB0-MBn. As the number of banks increases, therefore, the number of address signal lines increases. This results in an inevitable increase in the layout area for the address signal lines, thus increasing the area of the SDRAM 100.
Since the write operation or read operation of a selected bank and the refresh operation of non-selected banks are executed simultaneously, the peak of the consumed current of the entire device is relatively high.
When a self-refresh command is provided to each of the banks MB0-MBn, all of the banks perform the refresh operation simultaneously. The peak of the operational current in this case is relatively high. To supply the current in a stable manner, even at the time of such a peak, the power lines should have a relatively wide width. This also increases the area of the SDRAM 100.
No refresh operation is needed for any bank that has just finished a write operation or a read operation in accordance with the external address signals EA0-EA9. However, a bank that just finished a write operation or a read operation together with the other non-selected banks actually do undergo a refresh operation. This means that the bank consumes a wasteful current. In other words, the overall consumed current of the SDRAM 100 increases.
Accordingly, it is a first object of the present invention to provide a semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines.
It is a second object of the invention to provide a semiconductor memory device which suppresses the peak of the operational current of each bank, thus reducing the overall consumed current.
In one aspect of the present invention, there is provided a semiconductor memory device including a plurality of banks, a plurality of refresh address counters, a switch circuit, and a plurality of address holding circuits. Each of the plurality of banks performs a write operation and read operation according to an external address signal and a refresh operation according to a refresh address signal. The plurality of refresh address counters generate a plurality of refresh address signals associated with the plurality of banks in response to a refresh request signal. The switch circuit is connected to the plurality of refresh address counters and selectively outputs the external address signal and a refresh address signal generated by one of the plurality of refresh address counters in accordance with the refresh request signal. Each of the plurality of address holding circuits is connected between the switch circuit and the plurality of banks, holds one of the refresh address signals and the external address signal outputs from the switch circuit, and supplies the held address signal to an associated one of the banks.
In another aspect of the present invention, there is provided a method of refreshing a semiconductor memory device having a plurality of banks. The method includes generating a plurality of refresh address signals associated with the plurality of banks, supplying the plurality of refresh address signals in a time-divisional manner, holding a refresh address signal to be provided to an associated one of the banks, and refreshing the associated one of the banks in accordance with the held refresh address signal.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.